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Recruitment Notice
Job Titles
   Senior ASIC modeling and simulation engineer
   Senior ASIC design engineer
   Senior ASIC verification engineer
   RFIC design Manager
   Senior CMOS RF/Analog IC Designer
   Senior Analog IC design engineer
   Senior Research Engineer
   SOC Architect
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High-end recruitement
 
Job Title
 
Senior ASIC verification engineer (1 opening)
Location: Santa Clara, CA
Responsibilities:  
Architect and implement the system, chip, and module level verification strategy and infrastructure of a data communication chipset. Responsible for writing test plans, carrying out test case development, analyzing test failures, and aiding in debugging logic designs.
 
Qualifications:

1.Bachelor's Degree or higher in Computer Science, Electrical Engineering, Telecommunications or equivalent, with 5+ years experience in ASIC verification.
2.In-depth knowledge and experience with data communication chipset design and implementation.
3.Ability to work in a team environment; be self motivated and inclined to take initiative; possess excellent communication skills.