|
 |
 |
|
|
| |
| Job Title |
 |
| |
| Senior backend engineer (2 openings)
|
| Location: |
Shenzhen, China |
| Responsibilities: |
|
| Responsible for physical architecture implementation of large, complex, high-performance CMOS chips, focus on physical design, partitioning, floorplanning, physical verification and reliability verification. |
| |
| Qualifications: |
1.Bachelor's Degree or higher in Electrical Engineering or equivalent.
2.3+ years experience on physical design and at least successfully tapeout one 90nm or 65nm chip.
3.Experienced in Place & Route timing closure, synthesis, Static Timing Analysis.
4.A solid understanding of synthesis with Synopsys Design Compiler, timing driven layout and post-layout timing analysis with PrimeTime of deep sub-micron designs is essential.
5.Ability to work in a team environment; be self motivated and inclined to take initiative; possess excellent communication skills.
6.Bi-lingual Mandarin is preferred.
|
|
|
| |
|
|
