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Nerwork Access Terminal
   BVT (Broadband Video    Terminal)
Hi3510
Hi3511
  STB (Set Top Box)
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H.264 Encoding and Decoding Processor
 
Key Features

Embedded Processor

· ARM926EJ-S, 32-bit RISC processor, Harvard architecture
· 16 KB instruction cache and 16 KB data cache
· 2 KB tight coupled instruction memory
· Built-in MMU for open OS
· Up to 264 MHz

Video Codec
· H.264 Main Profile@Level3.0 encoding and decoding
· H.264 Baseline Profile@Level3.0 encoding and decoding
· MJPEG/JPEG Baseline encoding and decoding

Video Codec Performance
· Dual stream encoding (H.264/MJPEG)
· Main stream is up to 60fps@D1 or up to 240fps@CIF
· Sub-stream is up to 60fps@CIF or up to 240fps@QCIF
· H.264/MJPEG decoding is up to 25fps@1.3Mpixls
· H.264/MJPEG encoding and decoding simultaneously is up to 30fps@D1
· 300M pixels MJPEG/JPEG encoding is up to 5 fps
· CBR/VBR bit rate control, 16 Kbit/s to 20 Mbit/s

Image Processing
· De-interlace pre-processing
· Video/Image scaling
· Four areas OSD overlay for video input
· Four layers of OSD overlay for video output
· Contrast stretch and color intensification
· Video blanking of four areas
· Macro block level information output for flexible motion detection
· Pre-process for noise reduction

Audio Encoding and Decoding
· Various audio and voice codec with software
· Up to eight channels of real-time audio encoding and decoding
· The voice talk-back

Security Engine
· Implementing various encryption/decryption algorithms such as AES, DES, and 3DES through the hardware
· Proprietary Digital watermark

Video Interface
· Input
  – 4channel 27/54MHz BT.656/601 YCrCb 4:2:2, 8 bits. Each interface supports two channels of BT.656 multiplex video input
  – SMPTE296M 720P, YC 4:2:2, 16 bits
  – CCD and CMOS digital interfaces

·Output
  – BT.656. YCrCb 4:2:2, 8 bits

Audio Interface
· I2S x 2
  – 8, 16 or 32 bits
  – 4 KHz–48 KHz sample frequency

Peripheral Interface
· PCI V2.3
  – Compatible with the miniPCI
  – Supporting the master, slave mode
· UART x 3
· IR
· I2C
· SPI, master and slave mode
· GPIO
· SDIO2.0
· USB 1.1 Host
· USB 2.0 OTG
· MII Interface ,10/100Mbit/s duplex
· RTC, independent supply power

Memory Interface
· DDR2 SDRAM interface
  – 16 or 32 bit
  – Up to 512 MB
· NOR Flash interface
  – 8 bit
  – 2 Bank, each up to 32 MB

SDK
· Linux-based SDK
· High performance H.264 PC decoding library

Power Consumption
· 800 mW typical power consumption
· Multiple levels of power-down modes

Operating voltage
· 1.2 V for core
· 3.3 V for IO with 5v-tolerance
· 1.8 V for DDR2 DRAM I/O

Package
· 441-pin TFBGA
· 19 mm x 19 mm, 0.8 mm pitch


Functional Block Diagram



The Hi3511 video chip with ARM926EJS CPU core provides a high performance solution to accelerate the image and video related applications such digital video recoder, IP Camera, and real-time video communication. The Hi3511 is highly integrated and programmable and supports multiple video codec protocols. The Hi3511 also provides various peripherals interface.

The video codec engine supports various real-time encoding and decoding protocols such as the H.264 Main/Baseline Profile, MJPEG, and JPEG. It also supports that the H.264 encoding and decoding operations (with the 30fps@D1 frame rate) are performed simultaneously. The MJPEG and the JPEG support up to three-mega-pixel encoding. The powerful encoding algorithm of the H.264 MainProfile greatly improves the video quality and provides the field encoding or the frame encoding flexibly to adapt to the different display terminals. The videocodec engine also supports dual stream video encoding (H.264/MJPEG).

The image processing engine provides functions such as the De-interlace algorithm processing and the flexible motion detection and supports the video/image scaling and the OSD overlay.
 
Applications

· DVS (digital video server)
· DVR (digital video recorder)
· IP Camera
· PC digital video recorder






8CIF PC Card Based on the Hi3511