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| Narrowband Network |
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| What is the maximum switching capacity of the SD529 V3.0? What about the supported rates? |
| Can the SD526 operate in a normal state under 3.3 V voltages? |
| Does the SD507BC SLIC provide ringing function? |
| How is the interface level required by the SD539 V1.1? |
| How can we implement the 2-bit switching by using the SD539v1.1? |
| How many channels of E1 signals does the SA527V1.2 provide? |
| Why the chip neither can be reset nor modify other registers even if the SA527V1.2 reset register is written as 00h? |
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| Optical Network |
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| What about the ports and switching capacity supported the SD576V1.0? |
| Does the SD548V1.1 require frame or multi-frame synchronization signal for reception? |
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| Optical Network |
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| Why do the overflow alarms of the error code counters B3, B2, B1, RLREI and RPREI of the SD575V1.0 remain after refresh? |
| How many channels of overhead can be processed by the SD531? |
| Why cannot the SD519A be reset automatically after the Rx FIFO is overflowed? |
| If the SD518 writes to the Channel Cross Register when the GCLK is disabled, and then enable the GCLK to read the cross register, an error is reported. Why is this? |
| How many channels of crossover can the SD536 implement? |
| The SD528 has two status registers that are the same, one of which is read-only, and the other is read/write. What is the difference between them? |
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What is the maximum switching capacity of the SD529V3.0? What about the supported rates? |
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The SD529V3.0 supports 4K 4K timeslot switchover. The rate can be configured as 8.192 Mbit/s for UHW and 16.384Mbit/s for DHW. |
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Can the SD526 operate in a normal state under 3.3 V voltages? |
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The level is designed to be 5V for the I/O interfaces and 3.3 V for internal operation. If the 5V pads are connected to a 3.3 level, the I/O interfaces can work normally as well. However, the delay of the interfaces becomes longer, so extra delay should be taken into consideration for design. Since the operating frequency of the SD526A is low (2.048 MHz), the delay does not cause any serious problems. There are some successful cases in this condition. |
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Does the SD507BC SLIC provide the ringing function? |
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No, the SD507BC SLIC does not provide the ringing function. A separate ringing module is required. |
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How is the interface level required by the SD539 V1.1? |
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All input level for the SD539V1.1 is 5V/3.3V compatible LVTTL, the output level is CMOS level.The SD539V1.1 can receive 5V/3.3V TTL or CMOS levels, and output TTL levels that can drive 5V/3.3V devices and 3.3V devices. |
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How can we implement the 2-bit switching by using the SD539V1.1? |
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The SD539V1.1 must work in switch mode 1 (8Mbit/s UHW is switched into 8Mbit/s DHW). When the rates for UHM and DHM are both 8 Mbit/s, set the control register to 00H (switch mode 1) and Mod_Sel[1:0] to 00 (32 Mbit/s UHW is switched into 32 Mbits/s DHW). In this way, the 2-bit switching can be implemented. |
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How many channels of E1 signals does the SA527V1.2 provide? |
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The SA527V1.2 provides an LIU interface with eight channels of E1 signals. |
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Why the chip neither can be reset nor modify other registers even if the SA527V1.2 reset register is written as 00h? |
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The reset register should be written with FFh for reset. To modify other registers, it must be written with 00h. |
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What about the ports and switching capacity supported the SD576V1.0? |
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The SD576V1.0 provides up to 27 100 Mbps network ports for full line rate switching. The switching capacity reaches 5.4 Gbps and packet processing capacity reaches 8.035 Mpps. |
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Does the SD548V1.1 require frame or multi-frame synchronization signals for reception? |
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No, the signals are not required. The SD548V1.1 is integrated with the automatic search circuit for frame or CAS multi-frame synchronization. |
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Why do the overflow alarms of the error code calculators B3, B2, B1, RLREI and RPREI of the SD575V1.0 remain after refresh? |
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The alarm generation is controlled by both inner counters and outer counters. After the refresh once, only the inner counters are cleared. The alarms cannot be cleared until the counters are refreshed twice. |
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How many channels of overhead processing can the SD531 perform? |
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The SD531 can perform Regenerator Section Overhead processing to two channels of STM-1 or one channel of STM-4. |
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Why cannot the SD519Abe reset automatically after the Rx FIFO is overflowed? |
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Monitor the RxFIFO status, that is, monitor the 0x0c register. If an RxFIFO overflow is detected, write 0x80 and then 0x00 to the 0x0c register to reset the SD519A. |
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If the SD518 writes to the Channel Cross Register when the GCLK is disabled, and then enable the GCLK to read the cross register, an error is reported. Why is this? |
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When the GCLK is enabled, the SD518 must read the register after a delay so that it can get the accurate value. For the security purpose, the delay should be as long as 50ms. |
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How many channels of crossover can the SD536 implement? |
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The SD536 can implement 32 32 (4 bits) cross connection array in two modes:
1. Cross by channel, 32 32 (4 bits) VC, a 4-level crossover.
2. Cross by timeslot, 32 32 (4 bits) VC, a 12-level crossover. |
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The SD528 has two status registers that are the same, one of which is read-only, and the other is read/write. What is the difference between them? |
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The read-only register provides real-time alarms. It maintains the value after the alarm is read.
The read/write register provides historical alarms. It is cleared after the alarm is read, that is, the register is written with 0. It cannot be written externally. |
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