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Processor Core
• Arm Cortex-A7 MP2@900 MHz, 32 KB I-cache, 32 KB D-cache, and 256 KB L2 cache
• Neon acceleration, with an integrated FPU
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Video Encoding and Decoding
• H.265 Main Profile, Level 5.1
• H.264 Baseline/Main/High Profile, Level 5.1
• I-/P-slice supported for H.265/H.264 encoding and decoding
• JPEG Baseline
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Video Encoding and Decoding Performance
• Maximum resolution for H.265/H.264 encoding and decoding: 2688 x 1600
• H.265/H.264 encoding and decoding performance:
− 2688 x 1600@30 fps + 1024 x 576@30 fps encoding
− 2688 x 1600@30 fps decoding
• Maximum resolution for JPEG encoding and decoding: 8192 x 8192
• Maximum JPEG encoding and decoding performance: 4000 x 3000 fps
• Multiple bit rate control modes such as CBR, VBR, and FIXQP
• Maximum bit rate for H.265/H.264 encoding output: 100 Mbit/s
• Encoding of eight ROIs
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VI
• 4-lane image sensor serial input, with the MIPI, sub-LVDS, and HiSPI interfaces
• Division of the 4-lane MIPI sensor input into two groups of 2-lane MIPI inputs
• Maximum resolution of the first input: 2688 x 1600; maximum resolution of the second input: 2048 x 1536
• 10-/12-/14-bit Bayer RGB DC timing VI
• BT.656 and BT.1120 video input in YUV format
• One YUV input through the MIPI
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ISP and Image Processing
• Multi-channel TDM for processing 2-channel sensor video input
• Adjustable 3A functions (AE, AWB, and AF)
• FPN removal
• 2-frame WDR exposure, local tone mapping, strong light suppression, and backlight compensation
• Defect pixel correction (DPC) and lens shading correction (LSC)
• Multi-level 3DNR, which removes motion smearing and chroma noise and provides excellent image effects in low illumination
• 3D-LUT color adjustment
• Image dynamic contrast enhancement and edge enhancement
• CAC and purple fringe removal
• Dehaze
• 6DoF DIS (based on video or gyro information) and rolling-shutter correction
• Lens GDC
• Image rotation by 90° or 270°
• Image mirroring and flipping
• Multi-channel 1/15.5x–16x scaling for output
• OSD overlaying of up to eight regions before encoding
• ISP tuning tools on the PC
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Graphics Processing
• 2D graphics acceleration
• Maximum output resolution: 1920 x 1080.
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VO
• Overlay of two layers (video layer and graphics layer)
• HDMI 1.4 interface, with the maximum output of 1920 x 1080@60 fps
• 4-lane MIPI DSI output
• 6-/8-/16-/18-/24-bit digital LCD interface
• BT.656/BT.1120 interface
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Audio Interfaces
• Integrated audio codec, supporting 16-bit audio input and output
• Single-end dual-channel input and stereo output
• I2S interface, connected to external audio codec
• HDMI audio output
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Audio Encoding and Decoding
• Multi-protocol voice encoding and decoding implemented on software
• Audio encoding formats such as AAC/G.711/G.726
• Audio VQE processing
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Security Engine
• AES, DES, and 3DES encryption and decryption algorithms implemented on hardware
• RSA 1024/2048/4096 signature verification algorithms implemented on hardware
• HASH_SHA1/224/256/384/512 and HMAC_SHA1/224/256/384/512 tamper-proofing algorithms implemented on hardware
• Built-in 8 KB OTP storage space
• Built-in hardware true random number generator
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Peripheral Interfaces
• 2x SDIO 3.0 interfaces. One of them can be connected to the SD3.0 card.
• 1x USB 2.0 port, supporting the configurable host or device mode
• Output of the internal POR signal
• Independent battery for the built-in RTC
• Integrated 2-channel LSADC
• I2C, SPI, and UART interfaces
• 1x IR interface
• 3x PWM interfaces
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Memory Interfaces
• Embedded 1 Gb DDR3L SDRAM
• SPI NOR flash interface
− 1-/2-/4-wire mode
− 3-/4-byte address mode
− Maximum capacity: 256 MB
• SPI NAND flash interface
− Up to 24-bit/1 KB ECC performance
− Maximum capacity: 1 GB
• eMMC 4.5 interface
− 4-bit data width
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Boot
• Booting from the SPI NOR flash memory, SPI NAND flash memory, or eMMC
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Image Burning Mode
• Image burning over UART 0
• Image burning over the SD card
• Image burning over the USB device
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SDK
• Linux+HUAWEI LiteOS dual-system solution
• High-performance iOS/Android-based H.265 decoding library
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Physical Specifications
• Operating voltages
− 0.9 V core voltage
− 1.8 V/3.3 V I/O voltage
− 1.35 V voltage for the DDR3L SDRAM interface
• Package
− Body size of 14 mm x 13 mm, 306 pins, 0.65 mm ball pitch, TFBGA RoHS package