Chipsets

Hi3536CV100

Targeted at multi-channel HD NVRs, Hi3536CV100 combines Arm Cortex-A7 dual-core processor with video decoding and processing engines and algorithms. Together with HD outputs and peripheral interfaces, this professional SoC powers customer products with the performance and picture quality they need at lower eBOM costs.

Arm Cortex-A7 dual-core processor

4-channel 3M@20 fps H.265/H.264 decoding

HDMI/VGA HD output

Key Features

  • Processor Core

    • ARM Cortex A7 dual-core@1.3 GHz
    − 32 KB L1 I-cache, 32 KB L1 D-cache
    − 256 KB L2 cache
    − NEON and FPU
  • Video Encoding Decoding Protocols

    • H.265 Main Profile, Level 4.0 encoding
    • H.265 Main Profile, Level 5.0 decoding
    • H.264 Baseline/Main/High Profile, Level 4.1 encoding
    • H.264 Baseline/Main/High Profile, Level 5.1 decoding
    • MPEG-4 SP, L0–L3/ASP L0–L5 decoding
    • MJPEG/JPEG baseline
  • Video Encoding Decoding

    • H.265/H.264/JPEG encoding and decoding of multiple streams
    − 4x 1080p@30 fps H.265/H.264 decoding
    − 8x 720p@30 fps H.265/H.264 decoding
    − 16x D1@30 fps H.265/H.264 decoding
    − 1x 1080p@ 30 fps H.265/H.264 encoding
    − 4x 1080p@30 fps JPEG decoding
    • Constant bit rate (CBR) mode, variable bit rate (VBR) mode, FIXQP mode, adaptive variable bit rate (AVBR) mode, and QpMap mode Maximum 40 Mbit/s output bit rate
    • ROI encoding
    • Color-to-gray encoding
  • Intelligent Video Analysis

    • Integrated IVE, supporting various intelligent analysis applications such as motion detection, perimeter defense, and video diagnosis
  • Video and Graphics Processing

    • Deinterlacing, sharpening, 3D denoising, dynamic contrast improvement, and demosaic Anti-flicker for output videos and graphics
    • 1/15x to 16x video scaling
    • 1/2x to 2x graphics scaling
    • Four Cover regions
    • OSD overlaying of eight regions
  • Audio Encoding Decoding

    • ADPCM, G.711, and G.726 hardware audio encoding Software audio encoding and decoding complying with multiple protocols
  • Security Engine

    • AES, DES, and 3DES algorithms implemented by hardware
  • Video Interfaces

    • VO interfaces
    − One HDMI 1.4b output interface with the maximum output of 3840 x 2160@30 fps
    − One VGA HD output interface with the maximum output of 1080p@60 fps
    − Two independent HD output channels (DHD0 and DHD1), output over any HD interface (HDMI or VGA)
    − 36-picture output for DHD0, maximum output of 3840 x 2160@30 fps
    − 16-picture output for DHD1, maximum output of 1080p@60 fps
    − One CVBS SD output interface
    − Three full-screen GUI graphics layers in ARGB1555 or ARGB8888 format for two HD channels and one SD channel
    − Two hardware cursor layers in ARGB1555 or ARGB8888 format (configurable) with the maximum resolution of 256 x 256
  • Audio Interfaces

    • Two unidirectional I2S/PCM interfaces
    − One input interface, supporting 16-channel multiplexed input
    − One output interface, supporting dualchannel output
    − 16-bit audio inputs and outputs
  • Ethernet Ports

    • Two gigabit Ethernet ports
    − RGMII, RMII, and MII modes
    − 10/100 Mbit/s half-duplex or full-duplex
    − 1000 Mbit/s full-duplex
    − TSO for reducing the CPU usage
  • Peripheral Interfaces

    • Two SATA 3.0 interfaces
    − PM
    − eSATA Two USB 2.0 host ports, supporting the hub
    • Three UART interfaces, one of which supporting four wires
    • One SPI, supporting two CSs
    • One IR interface
    • One I2C interface
    • Multiple GPIO interfaces
  • Memory Interfaces

    • One 16-bit DDR3 SDRAM interface
    − Maximum frequency of 933 MHz
    − ODT
    − Maximum capacity of 1 GB
    − Automatic power consumption control
    • SPI NOR/NAND flash interface
    − 1-/2-/4-wire SPI NOR/NAND flash
    − Two CSs, connected to different types of flash memories
    − Maximum capacity of 64 MB for each CS (for the SPI NOR flash)
    − Maximum capacity of 512 MB for each CS (for the SPI NAND flash)
    − 2 KB/4 KB page size (for the SPI NAND flash)
    − 8-bit/1 KB or 24-bit/1 KB ECC (for the SPI NAND flash)
    • Embedded 4 KB BOOTROM and 16 KB SRAM
  • RTC with an Independent Power Supply

    • Independent battery for supplying power to theRTC
  • Configurable Boot Modes

    • Booting from the BOOTROM
    • Booting from the SPI NOR flash
    • Booting from the SPI NAND flash
  • SDK

    • Linux 3.18-based SDK
    • Audio encoding and decoding libraries complying with various protocols
    • High-performance H.265/H.264 PC decoding library
  • Physical Specifications

    • Power consumption
    − Typical power consumption of 2.0 W
    − Multi-level power consumption control
    • Operating voltages
    − 0.9 V core voltage
    − 1.0 V CPU voltage
    − 3.3 V I/O voltage
    − 1.5 V DDR3 SDRAM interface voltage
    • Package
    − RoHS, TFBGA
    − Lead pitch of 0.65 mm (0.03 in.)
    − Body size of 15 mm x 15 mm (0.59 in. x 0.59 in.)
    • Operating temperature ranging from 0°C (32°F) to 70°C (158°F)

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