Hi3921EV100

• Peak rate at the physical layer: 0.507 Mbit/s
• Receiver sensitivity: > 0.2 mVpp

• Static power consumption (SoC): ≤ 50 mW

• Implementation of the IEEE 1901.1 standard, enabling the SoC to interconnect and communicate with other equivalent SoCs
• Three frequency bands: 1.6–6 MHz, ≤ 500 kHz, and ≤ 150 kHz, with subcarriers configurable
• OFDM, supporting BPSK and QPSK modulation modes
• Powerful forward error correction (FEC) and cyclic redundancy check (CRC) capabilities

• TDMA and CSMA/CA, offering the conflict avoidance mechanism
• Data segmentation and reassembly, improving transmission efficiency
• Data retransmission mechanism
• Four levels of QoS, meeting the service quality requirements of different services

• Automatic fast networking within 10 seconds in a typical scenario with 500 nodes on a 2-layer network
• Dynamic routing and multi-path addressing

• High-performance Cortex-M3 processor operating at 200 MHz
• Embedded 256 KB SRAM

• 1x SPI, 1x I2C interface, 2x UART interfaces, 1x flash interface, 2x PGA interfaces, 6x GPIO interfaces, 1x 12-bit 4-channel AD input, and 1x PWM interface