Hi3716MV430C/S/T

• High-performance Arm Cortex-A7 processor
• Built-in I-cache, D-cache, and L2 cache
• Hardware Java acceleration
• Floating-point coprocessor

• DDR3/DDR3L interface
− Maximum capacity of 512 MB for external DDR SDRAM or of 128 MB/256 MB for built-in DDR SDRAM
− 16-bit data width
• SPI NOR flash/SPI NAND flash, parallel SLC NAND flash, or SPI NOR flash+a parallel SLC NAND flash

• H.265 Main/Main 10@Level 4.1 High tier
• H.264 BP/MP/HP@Level 4.2; MVC
• MPEG-1
• MPEG-2 SP@ML and MP@HL
• MPEG-4 SP@Levels 0–3, ASP@Levels 0–5, GMC,
• MPEG-4 short header format (H.263 baseline)
• AVS Jizhun Profile@Level 6.0 and AVS+
• VC-1 SP@ML, MP@HL, and AP@Levels 0–3
• VP6/VP8
• 1-channel 1080p@60 fps decoding

• JPEG decoding, supporting at most 64 MP

• MPEG L1/L2
• Dolby Digital/Dolby Digital Plus decoder-converter
• AAC-LC and HE-AAC V1/V2 decoding
• Downmixing, resampling, and automatic volume control TS Demultiplexing/PVR
• One built-in DVB-C QAM demodulator, compliant with J.83 A/B/C
• Up to 4-channel TS input, or 3-channel TS+1-channel tuner input
• Up to 1-channel TS output
• Up to 96 hardware PID channels
• Recording of scrambled and non-scrambled streams

• Advanced CA feature
• OTP
• AES, DES, and 3DES data encryption and decryption

• Hardware TDE
• 3-layer OSD
• Two video layers
• 16-bit and 32-bit color depth
• Full-hardware anti-aliasing and anti-flicker
• IE, NR, and CCS
• DEI

• PAL, NTSC, and SECAM standard outputs, and forcible standard conversion
• Aspect ratio of 4:3 or 16:9, forcible aspect ratio conversion, and free scaling
• 1080p50(60)/1080i/720p/576p/576i/480p/480i outputs
• HD and SD output for the same source
• Color gamut compliant with the xvYCC (IEC 61966-2-4) standard
• HDMI 1.4b with HDCP 1.4
• Analog video interfaces
− One CVBS interface
− One built-in VDAC
− VBI
• Audio interface
− Audio-left and audio-right channels
− S/PDIF interface
− One built-in ADAC
− Output voltage swing up to 2 Vrms

• Two USB 2.0 host interfaces (integrated with PHY)
• One 10/100 Mbit/s adaptive Ethernet interface with integrated FE PHY
• One UART interface
• Two SCIs that support T0/T1/T14 protocols, with one SCI supporting 5 V and 3 V cards
• One IR receiver
• One LED and keypad control interface
• Three I2C interfaces
• Multiple groups of GPIO interfaces

• Faster booting
• Integrated dedicated standby processor, with chip standby power less than 30 mW
• TFBGA package
• 2-layer or 4-layer PCB routing