Chipsets

Hi3521DV200

This latest design powers multi-channel HD/UHD digital video recorders. With powerful processor and inference engine, multiple intelligent algorithm applications are now a reality. Integrated MIPI D-PHY inputs break through predecessor limits in video input performance and capability. Improving on the H.265 video codec engine and video image processing algorithm, this SoC provides analog HD DVR solutions for multiple peripheral devices and high-speed interfaces for wide adoption in analog HD surveillance markets.

Arm Cortex-A7 quad-core processor@1.2 GHz

8-channel 1080p15 H.265/H.264 encoding and eight 1080p30 real-time video inputs

NNIE with 0.8 TOPS of computing power

Key Features

  • Processor Cores

    • ARM Cortex-A7 quad-core@1.2 GHz
    − 32 KB L1 I-cache and 32 KB L1 D-cache
    − 256 KB L2 cache
    − NEON/FPU
  • Multi Protocol Video Codec

    • H.265 Main Profile, Level 5.0 encoding
    • H.265 Main Profile, Level 5.0 decoding
    • H.264 Baseline/Main/High Profile, Level 5.1 encoding
    • H.264 Baseline/Main/High Profile, Level 5.1 decoding
    • MJPEG/JPEG Baseline encoding and decoding
  • Video Codec

    • H.265/H.264&JPEG multi-stream encoding and decoding performance:
    − 4 x 1080p@30 fps H.265/H.264 encoding+4 x D1@30 fps H.265/H.264 encoding+4 x 1080p@30 fps H.265/H.264 decoding+4 x 1080p@2 fps JPEG encoding
    − 8 x 1080p@15 fps H.265/H.264 encoding+8 x D1@30 fps H.265/H.264 encoding+8 x 1080p@15 fps H.265/H.264 decoding+8 x 1080p@2 fps JPEG encoding
    • Seven bit rate control modes, including CBR, VBR, AVBR, CVBR, FIXQP, QPMAP, and QVBR
    • Output bit rate up to 20 Mbit/s
    • ROI encoding
    • Color-to-gray encoding
  • SVP

    • NNIE
    − Multiple neural network options
    − 0.8 TOPS computing performance
    − Complete APIs and toolchains
    − Multiple applications such as face detection, facial recognition, object detection, and object tracking
    • IVE
    − Object tracking
    • MAU
    − Single-precision or half-precision floats
    − Feature vector comparison
  • Video and Graphics Processing

    • Pre-processing and post-processing including de-interlacing, sharpening, 3DNR, DCI, and mosaic
    • Anti-flicker for video and graphic outputs
    • Video scaling (1/15x to 16x)
    • Graphics scaling (1/2x to 2x)
    • Up to four Cover regions
    • Up to 8-region OSD overlay
  • Video Interfaces

    • VI interfaces
    − Four MIPI D-PHY interfaces
    ° Four lanes supported by MIPI0/1
    ° Two lanes supported by MIPI2/3
    ° Two operating modes: 2 x 4 lanes and 4 x 2 lanes
    ° Up to 1.5 Gbit/s per lane
    ° Single input, two multiplexed inputs, or four multiplexed inputs
    ° Multiplexed as four 8-bit BT.656 interfaces
    − Every two BT.656 interfaces can form one 16-bit BT.1120 interface.
    − Both BT.656 and BT.1120 interfaces support dual-edge sampling at 148.5 MHz.
    − Up to 16 VI channels
    − 8-channel online video scaling
    − The source image and the scaled image can be output at the same time.
    − Maximum input performance: 8-channel 1080p@30 fps (or 4M/5M/4K images with the same data volume)
    • VO interfaces
    − One HDMI 1.4b output interface with the maximum output of 3840 x 2160@30 fps
    − One VGA HD output interface at up to 2560 x 1600@60 fps
    − One BT.1120/BT.656 digital output interface, with the respective maximum output of 1080p@60 fps/1080p@30 fps
    − One CVBS SD output interface, supporting the PAL/NTSC standard output
    − Two independent HD VO channels (DHD 0 and DHD 1)
    ° Two HD interfaces with display fromdifferent sources
    ° DHD 0 supports 16-picture display.
    ° DHD 1 supports 16-picture display.
    − One independent SD output channel (DSD 0)
    − One PiP layer, which can be overlaid with DHD 0 or DHD 1
    − Two graphics layers in ARGB1555, ARGB4444, or ARGB8888 format for DHD 0 and DHD 1, respectively
    − One special graphics layer, which supports CLUT 2/CLUT 4 and can be bound to DHD 0, DHD 1, or DSD 0
    − One hardware cursor layer in ARGB1555, ARGB4444, or ARGB8888 format (configurable) with a maximum resolution of 256 x 256
  • Audio Interfaces

    • Three unidirectional I2S/PCM interfaces
    − Two inputs, supporting 20 multiplexed inputs
    − One output, supporting dual-audio channel output
  • ETH Interfaces

    • One 100 Mbit/s Ethernet interface
    − Integrated FE PHY
    − 10/100 Mbit/s half-duplex or full-duplex
    − TSO for reducing the CPU overhead
  • Security Engine

    • AES 128/192/256-bit encryption and decryption algorithms
    • RSA 2048/4096-bit encryption and decryption algorithms
    • SHA256/HMAC_SHA1/HMAC_SHA224/HMAC _SHA256
    • OTP, providing 28-kbit user space to burn images
    • Hardware-based true random number generator
    • Secure boot
    • Secure memory isolation
  • Peripheral Interfaces

    • Two SATA 3.0 interfaces
    • Three USB 2.0 host interfaces
    • Five UART interfaces, one of which supports the 4-wire mode
    • Two SPI interfaces
    • One IR interface
    • Two I2C interfaces
    • Multiple GPIO interfaces
  • Memory Interfaces

    • One 32-bit DDR4/DDR3 interfaces
    − Maximum DDR4 clock frequency: 1333 MHz
    − Maximum DDR3 clock frequency: 1066 MHz
    − Maximum capacity: 3 GB
    • One SD/MMC interface
    − eMMC 5.0
    − HS400 (150 MHz dual-edge)
    − SDIO 2.0 and SDIO 3.0
    − SD 2.0 card
    • SPI NOR flash and SPI NAND flash interfaces
    − Two CSs, which can be connected to different types of flash memories
    − For the SPI NOR flash:
    ° 1-, 2-, or 4-line mode
    ° 3- or 4-byte address mode
    ° Maximum capacity: 256 MB
    − For the SPI NAND flash:
    ° SLC flash
    ° 2 KB or 4 KB page size
    ° 8- or 24-bit ECC (ECC is in the unit of 1 KB.)
    ° Maximum capacity: 2 GB
  • RTC with Independent Power Supply

    The RTC can be independently powered by batteries.
  • Multiple Boot Modes

    • Boot from the BootROM
    • Boot from the SPI NOR flash
    • Boot from the SPI NAND flash
    • Boot from the eMMC
  • SDK

    • Linux SMP (32-bit)
    • Audio codec libraries that support multiple protocols
    • High-performance PC decoding library basedon H.265/H.264
  • Chip Physical Specifications

    • Power consumption
    − Power consumption in typical scenarios (4- channel 1080p@30 fps encoding+4-channel 1080p@30 fps decoding+deep learning intelligent algorithm): 3.3 W
    − Multi-level power consumption control
    • Operating voltages
    − Core voltage: 0.9 V
    − CPU voltage: 1.0 V
    − I/O voltage: 1.8 V/3.3 V
    − Voltage of the DDR4 interface: 1.2 V
    − Voltage of the DDR3 interface: 1.5 V
    • Package
    − ROHS, TFBGA
    − Ball pitch: 0.8 mm (0.03 in.)
    − Dimensions: 19 mm x 19 mm (0.75 in. x 0.75 in.) – Operating temperature: 0°C–70°C (32°F– 158°F)

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