Hi3516DV200 chip

• Arm Cortex-A7@ 900 MHz, 32 KB I-Cache, 32 KB D-Cache/128 KB L2 cache
• Neon acceleration, with an integrated FPU

• H.264 BP/MP/HP, supporting I-/P-frames
• H.265 MP, supporting I-/P-frames
• MJPEG/JPEG Baseline encoding

• Maximum resolution for H.264/H.265 encoding: 3072 x 1728/2688 x 1944 (with the width up to 3072 and height up to 1944)
• Real-time multi-stream H.264/H.265 encoding capabilities:
− 2688 x 1520@30 fps+720 x 576@30 fps
− 3072 x 1728@20 fps+720 x 576@20 fps
− 2688 x 1944@20 fps+720 x 576@20 fps
• JPEG snapshot at 5M (3072 x 1728/2688 x 1944)@5 fps
• Six bit rate control modes (CBR, VBR, FIXQP, AVBR, QPMAP, and CVBR)
• Intelligent encoding mode
• Up to 60 Mbit/s output bit rate
• Encoding of eight ROIs

• Intelligent video engine (IVE)
• A wide range of intelligent analysis applications, such as intelligent motion detection, perimeter defense, and video diagnosis

• 3DNR, image enhancement, and DCI
• Anti-flicker for output videos and graphics
• 1/15x to 16x video and graphics scaling
• Video and graphics overlaying
• Image rotation by 90°, 180°, or 270°
• Image mirroring and flipping
• OSD overlaying of eight regions before encoding

• 4x4 pattern RGB-IR sensor
• 3A functions (AE, AF, and AWB). Third-party 3A algorithms are supported.
• FPN removal and DPC
• LSC, LDC, and purple fringing correction
• Direction-adaptive demosaic
• Gamma correction, DCI, and color management and enhancement
• Region-adaptive dehaze
• Multi-level NR (BayerNR and 3DNR) and sharpening enhancement
• Local tone mapping
• Sensor built-in WDR
• 2F-WDR line/frame mode
• DIS
• Intelligent ISP tuning. PC-based ISP tuning tools are provided.

• Multi-protocol voice encoding and decoding implemented on software
• Compliance with the G.711, G.726, and ADPCM protocols
• Audio 3A functions (AEC, ANR, and AGC)

• AES/RSA encryption and decryption algorithms implemented on hardware
• HASH (SHA1/SHA256/HMAC_SHA1/HMAC_SHA256) algorithms implemented on hardware
• Integrated 32-kbit OTP storage space and random number generator

• Input
− 8-/10-/12-bit RGB Bayer DC timing video input. BT.1120 input is supported.
− MIPI, LVDS/sub-LVDS, and HiSPI
− Compatibility with mainstream HD CMOS sensors provided by Sony, ON Semiconductor, OmniVision, and Panasonic
− Compatibility with the electrical specifications of parallel and differential interfaces of various sensors
− Programmable sensor clock output
− Maximum input resolution: 3072 x 1728 or 2688 x 1944
• Output
− 6-/8-/16-bit LCD output
− BT.656/BT.1120 output

• Integrated audio codec, supporting 16-bit audio input and output
• Dual-channel MIC/line-in input
• Dual-channel line-out output
• I²S interface, connected to external audio codec

• POR
• Integrated high-precision RTC
• Integrated 4-channel LSADC
• 3x UART interfaces
• I²C, SPI, and GPIO interfaces
• 4x PWM interfaces
• 2x SDIO 2.0 interfaces
• 1x USB 2.0 host/device interface
• Integrated FE PHY, supporting TSO network acceleration
• Integrated power management controller (PMC)

• SDRAM interfaces
− DDR3/DDR3L interfaces with a maximum frequency of 900 MHz (1.8 Gbit/s)
− Maximum capacity of 4 Gbits for a single 16-bit DDR SDRAM
• SPI NOR flash interface
− 1-/2-/4-wire mode
− Maximum capacity: 256 MB
• SPI NAND flash interface
− 1-/2-/4-wire mode
− Maximum capacity: 1 GB
• eMMC 5.0 interface
− 4-/8-bit data width

• Booting from the SPI NOR flash memory, SPI NAND flash memory, or eMMC
• Secure boot

• Linux-4.9-based SDK
• High-performance H.264 PC decoding library
• High-performance H.265 PC, Android, and iOS decoding libraries

• Power consumption
− Typical power consumption of 900 mW in the 4M30/5M20 scenario
• Operating voltages
− 0.9 V core voltage
− 3.3 V I/O voltage (±10%)
− 1.5 V DDR3 SDRAM interface voltage
− 1.35 V DDR3L SDRAM interface voltage
• Package
− 12 mm x 13.3 mm, 279 pins, 0.65 mm ball pitch, TFBGA package