Designed for entry-level H.265 HD NVRs, Hi3536DV100 combines Arm Cortex-A7 processor with video decoding and processing engines and algorithms. Together with HD outputs and peripheral interfaces, this SoC powers customer products with the performance and picture quality they need at lower eBOM costs.

Arm Cortex-A7 processor

4-channel 3M@20 fps H.265/H.264 decoding

HDMI/VGA HD output

Key Features

  • Processor Core

    • Arm Cortex-A7 @850 MHz
    − 32 KB L1 I-cache, 32 KB L1 D-cache
    − 128 KB L2 cache
    − Neon and FPU
  • Video Encoding and Decoding Protocols

    • H.265 Main Profile, Level 4.1 decoding
    • H.264 Baseline/Main/High Profile, Level 4.2 decoding
    • JPEG Baseline encoding
    • MJPEG/JPEG Baseline decoding
  • Video Encoding and Decoding

    • H.265/H.264/JPEG multi-stream encoding and decoding
    − 4x 1080p@25 fps H.265/H.264 decoding
    − 4x 3M (2048 x 1536)@20 fps H.265/H.264 decoding
    − 4x 720p@30 fps JPEG decoding
  • Video and Graphics Processing

    • Sharpening and contrast strengthening
    • 1/15x to 16x video scaling
    • 1/2x to 2x graphics scaling
    • Cover regions
    • OSD overlaying
  • Audio Encoding and Decoding

    • Multi-protocol audio encoding and decoding implemented on software
  • Security Engine

    • AES, DES, and 3DES algorithms implemented on hardware
  • Video Interfaces

    • VO interfaces
    − One HDMI 1.4b output interface
    − One VGA HD output interface
    − HDMI/VGA outputs from the same source, with the maximum output of 1080p@60 fps
    − One HD video layer and 16-picture output
    − One HD PiP layer
    − One ARGB1555 or ARGB8888 HD graphics layer
    − One hardware cursor layer in ARGB1555 or ARGB8888 format (configurable) with the maximum resolution of 256 x 256
  • Audio Interfaces

    • Two unidirectional I2S/PCM interfaces
    − One dual-channel input
    − One dual-channel output
    − 16-bit audio inputs and outputs
    • Integrated with audio DAC
    − 48 kHz, 44.1 kHz, and 32 kHz sampling rates
    − Dual-channel line-out
  • Ethernet Interfaces

    • One fast Ethernet (FE) interface
    − Integrated with FE PHY
    − PHY, RMII, and MII interface modes
    − 10/100 Mbit/s half-duplex or full-duplex
    − TSO for reducing the CPU overhead
  • Peripheral Interfaces

    • One SATA 2.0 interface
    − PM
    − eSATA
    • Two USB 2.0 host interfaces, supporting the hub
    • Three UART interfaces, one of which supporting the 4-wire mode
    • One IR interface
    • One I2C interface
    • Multiple GPIO interfaces
  • Memory Interfaces

    • One 16-bit DDR3/DDR3L SDRAM interface
    − Maximum frequency of 800 MHz
    − ODT
    − Maximum capacity of 512 MB
    − Automatic power consumption control
    • SPI NOR/NAND flash interface
    − 1-/2-/4-wire mode
    − Two CSs, connected to different types of flash memories
    − Maximum capacity of 64 MB for each CS (for the SPI NOR flash)
    − Maximum capacity of 512 MB for each CS (for the SPI NAND flash)
    − 2 KB/4 KB page size (for the SPI NAND flash)
    − 8-bit/1 KB, 16-bit/1 KB, 24-bit/1 KB, or 28-bit/1 KB ECC (for the SPI NAND flash)
    • Embedded 4 KB BootROM
  • RTC with Independent Power Supply

    • Independent battery for supplying power to the RTC
  • Configurable Boot Modes

    • Booting from the BootROM
    • Booting from the SPI NOR flash
    • Booting from the SPI NAND flash
  • SDK

    • Linux 4.9-based SDK
    • Audio encoding and decoding libraries complying with multiple protocols
    • High-performance H.265/H.264 PC decoding library
  • Physical Specifications

    • Power consumption
    − Typical power consumption of 1.6 W
    − Multi-level power consumption control
    • Operating voltages
    − 1.1 V core voltage
    − 1.26 V CPU voltage
    − 3.3 V I/O voltage
    − 1.5 V DDR3 SDRAM/1.35 V DDR3L SDRAM interface voltage
    • Package
    − RoHS, TFBGA
    − Ball pitch of 0.65 mm
    − Body size of 13 mm x 13 mm
    • Operating temperature: 0°C–70°C

View More Products


HV2 Product Support Intro
Technical Support